1. Field of the Invention
The present invention relates to a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode and, more particularly, to a multi-bit pipeline ADC in which an operating mode is altered by controlling the number of stages in a pipeline and a signal path according to required resolution and operating frequency so that power consumption can be minimized.
2. Discussion of Related Art
In order to process an image signal in an imaging system, a small analog signal needs to be converted into a digital signal sensitive to a noise. The conversion of the analog signal into the digital signal is performed using an ADC.
Since image data output from a sensor is very minute, the imaging system requires a high-resolution ADC capable of distinguishing a small signal. In addition to the imaging system, communication systems and image processing/application systems, such as mobile communication devices, asynchronous digital subscriber loops (ADSLs), IMT-2000, digital camcorders, and High Definition Televisions (HDTVs), also require high-resolution ADCs that have a high resolution (12-/14-bit) and a high sampling rate of several tens of MHz.
Among the variety of known ADC structures, a flash ADC, a folding ADC, a subranging ADC, and a pipeline ADC are able to process signals at a high speed. In recent years, a pipeline ADC structure, which consumes low power and occupies a small area, has been widely used to satisfy both conditions of high-speed signal processing and a high resolution at the same time.
A conventional pipeline ADC may be classified into a single-bit structure, which decides 1 bit for each stage, and a multi-bit structure, which decides 2 bits or more for each stage. In general, a high-resolution pipeline ADC has adopted the multi-bit structure to a greater extent than the single-bit structure which requires many stages, because the multi-bit structure decides many bits at a first stage to lessen the influence of the next stage and reduce power consumption and an occupied area.
FIG. 1 is a circuit diagram of a conventional multi-bit pipeline ADC.
Referring to FIG. 1, the multi-bit pipeline ADC includes several stages, so that an analog input signal VIN passes through a sample-and-hold amplifier (SHA) 10 and is converted into a digital signal at each of stages ST1 to STn, and is output. For example, the stage ST1 includes a B-bit flash ADC 20 and a B-bit multiplying digital-to-analog converter (MDAC) 30. The B-bit flash ADC 20 receives an analog signal from a front stage, converts the analog signal into a digital signal, and outputs the digital signal. The B-bit MDAC 30 converts a difference between the digital signal output from the B-bit flash ADC 20 and the front-stage output signal into an analog signal and outputs the analog signal into the next stage.
In other words, the conventional multi-bit pipeline ADC includes one SHA 10 for an input terminal, an n+1 number of B-bit flash ADCs 20, and an n number of B-bit MDACs 30. In this case, the entire multi-bit ADC has a resolution of n*(B−1)+B.
However, when the conventional multi-bit pipeline ADC is designed for a predetermined operating speed and a resolution of one application or designed for the highest specifications of several applications and operates for a system having low specifications, the multi-bit pipeline ADC reduces power consumption by adjusting the amount of current. As a result, controlling the entire current becomes complicated, and optimizing the multi-bit pipeline ADC in terms of power consumption is difficult.
Specifically, the accuracy of a signal output from an output terminal of an i-th MDAC should be on the level of
      1          2                                    (                          n              -              i                        )                    *                      (                          B              -              1                        )                          +        B              .When a clock frequency of the entire ADC is referred to as “fs”, since the operating speed of an amplifier, which is required by the i-th MDAC, is proportional to In(2(n−i)*(B·1)+B), the i-th MDAC is designed to output a signal with the same accuracy at a higher speed than an i+1-th MDAC by
                              (                      n            -            i                    )                *                  (                      B            -            1                    )                    +      B                                (                      n            -            i            -            1                    )                *                  (                      B            -            1                    )                    +      B        .
For instance, assuming that n=3 and B=3, since the entire ADC has a 9-bit resolution, and a first-stage MDAC should output a signal with 7-bit accuracy and a second-stage MDAC should output a signal with 5-bit accuracy, the first-stage MDAC is designed to operate faster than the second-stage MDAC by 7/5(140%).
However, when the conventional multi-bit pipeline ADC is simultaneously used for several applications, the multi-bit pipeline may be designed for the highest specifications and operate for a system having low specifications. In this case, the multi-bit pipeline ADC reduces power consumption by adjusting the amount of current. For example, when the multi-bit pipeline ADC using one ADC is required to operate at a speed of 50 MHz and have 10- and 8-bit resolution, the multi-bit pipeline ADC is designed for 10-bit resolution and utilizes most significant 8 bits for an 8-bit application. In this case, when the multi-bit pipeline ADC has the same operating speed of 50 MHz as in a 10-bit application, power consumption may be minimized by reducing the whole amount of current to about 80%. However, in the front-stage MDAC for outputting most significant bits (MSBs), capacitance and an amplifier are set to meet a 10-bit resolution. Thus, larger current is generated than in an amplifier that is actually designed for an 8-bit resolution, and a current control method becomes complicated. As a result, it is difficult to optimize the multi-bit pipeline ADC in terms of power consumption.
In other words, since the conventional multi-bit pipeline ADC has predetermined operating speed and resolution, when the multi-bit pipeline ADC is used for several applications at the same time, it is difficult to minimize power consumption under an operating condition of low specifications.